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| Ordering number : EN*5784 CMOS LSI LC895925 Signal Processing LSI for CD-R Drives Preliminaly Overview The LC895925 provides the following signal processing functions for CD-R drives: CD-ROM decoding/encoding (complete with ECC processing for the former), subcode decoding/encoding, CD encoding, ATIP decoding, CLV servo, and SCSI interface registers. * Buffer RAM sizes between 1 and 32 megabits (using 16bit DRAMs) * User control over sizes of CD main channel, C2 flag, and subcode areas in buffer RAM * Built-in batch transfer function for transferring entire CD main channel, C2 flag, or subcode area in a single operation * Built-in multiblock transfer function for transferring multiple blocks in a single operation Notes: 1. Using a SCSI master clock of 20 MHz with speeds up to 8x. 2. Using a SCSI master clock of 17.2872 MHz with speeds up to 4x. Features * CD-ROM decoding/encoding complete with error detection and error correction * Subcode decoding/encoding complete with error correction * ATIP decoding and CRC checking for both encoding and decoding * CLV servo control using ATIP data during encoding * CIRC code insertion and EFM modulation during encoding * Support for PCA random EFM output during encoding * Support for CD-ReWritable (CD-RW) Write Strategy signal output * Access to buffer RAM from microcontroller via LC895925 * Built-in SCSI interface * Speeds of 12x for decoding and 4x for encoding -- Frequencies Decoding: 17.2872 MHz Encoding: 17.2872 MHz without Write Strategy support 69.1488 MHz with Write Strategy support * Transfers speeds of 10 megabytes/s (synchronous) and 5 megabytes/s (asynchronous) with 16 80-ns DRAMs *1 Package Dimensions unit: mm 3153A-QFP160E [LC895925] SANYO: QIP160E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN D1997RM (OT) No. 5784-1/7 LC895925 Specifications Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Maximum power supply voltage I/O voltage Maximum power dissipation Operating temperature Storage temperature Solder resistance Symbol VDD max VI, VO Pd max Topr Tstg 10 seconds Ta 70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD+0.3 600 -30 to +70 -55 to +125 260 Unit V V mW C C C Permissible Operating Range at Ta = -30 to +70C, VSS = 0 V Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 4.5 0 typ 5.0 max 5.5 VDD Unit V V DC Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V Parameter Input high level voltage Input low level voltage Input high level voltage Input low level voltage Input high" level voltage Input low level voltage Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output low level voltage Input leak current Pull-up resistance The pin types above refer to the following groups. Symbol VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL VOL IIL RUP Conditions Ratings min 2.2 0.8 2.2 0.8 2.5 0.6 VDD - 2.1 0.4 VDD - 2.1 0.4 VDD - 2.1 0.4 0.4 -10 40 80 +10 160 typ max Unit V V V V V V V V V V V V V A k TTL levels, for pin types 1 and 6 TTL levels, for pin type 4, with pull-up resistors TTL levels, for pin 0 and 7, with Schmitt inputs IOH = -2 mA, for pin type 3 IOL = 2 mA, for pin type 3 IOH = -2 mA, for pin types 2, 4, and 6 IOL = 2 mA, for pin types 2, 4, and 6 IOH = -48 mA, for pin type 7 IOL = 48 mA, for pin type 7 IOL = 2 mA, for pin type 5 VI = VSS, VDD, for pin types 0, 1, 6, and 7 For pin types 4 and 5 Input (0) BCK, BICLKIN, BIDATAI, C2PO, LOCKIN, LRCK, PLLOUTIN, ROUGH, SBSO, SCOR, SDATA, WFCK, CS, RD, WR (1) SUA0 to SUA6, TEST0 to TEST6, X1EN, RESET Output (2) CLV+, CLV-, FSW (3) DATACKO, EFM, EFMG, EFMGATE0 to EFMGATE6, EXCK, LOCK, MCK, MON, PSUBSYNC, RA0 to RA9, SUBSYNC, CAS0 to CAS1, RAS0 to RAS1, ERROR, EXTACK, FRCK, LWE, UWE, OE Input/Output (4) D0 to D7, IO0 to IO15 (5) INT0 to INT1, SWAIT (6) ATIPSYNC, Reserve0 to Reserve5 (7) ACK, ATN, BSY, C/D, DB0 to DB7, DBP, I/O, MSG, REQ, RST, SEL Note: The XTAL0, XTAL1, XTALCK0, and XTALCK1 pins fall outside of these DC characteristic specifications. No. 5784-2/7 LC895925 Block Diagram *1 *2 *3 *4 *6 *7 *8 *9 *10 *11 *12 WFCK, SBSO, SCOR BCK, SDATA, LRCK, C2PO DB0 to DB7, DBP, BSY, MSG, SEL, RST, REQ, I/O, C/D ACK, ATN RD, WR, SUA0 to SUA6, CS D0 to D7 IO0 to IO15 RA0 to RA9, RAS0, RAS1, CAS0, CAS1, OE, UWE, LWE PLLOUTIN, ROUGH, LOCKIN, BICLKIN, BIDATAIN ERROR, LOCK, CLV+ (MDP), CLV- (MDS), MON, FSW SUBSYNC, PSUBSYNC, FRCK, EFM, EFMG, EFMGATE3 to EFMGATE0, EXTACK, DATACK0 No. 5784-3/7 LC895925 Pin Descriptions Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Pin Name VSS Reserve0 Reserve1 Reserve2 TEST1 XTALCK0 XTAL0 TEST2 MCK TEST3 XTALCK1 XTAL1 TEST4 VDD VSS CLV+ (MDP) CLV- (MDS) MON FSW VDD VSS PLLOUTIN ROUGH LOCKIN LOCK ERROR ATIPSYNC BIDATAI BICLKIN VDD IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 VDD VSS Type P B B B I I O I O I I O I P P O O O O P P I I I O O B I I P B B B B B B B B B P P Data signal pins for ROM encoder/decoder buffer RAM, with pull-up resistors Wobble signal carrier clock input pin Rough CLV servo wobble signal input pin CD decoder lock signal input pin CLV servo lock monitor pin ATIP parity error detection pin ATIP synchronization signal I/O pin Biphase data input pin Biphase data transfer clock input pin CLV servo signal output pins Reserved for future expansion (leave open) Reserved for future expansion (connect to ground) Reserved for future expansion (connect to ground) Test pin (connect to VSS) Crystal oscillator circuit input pin (17.2872 to 69.1488 MHz) Crystal oscillator circuit output pin Test pin (connect to VSS) Master Clock output pin Test pin (connect to VSS) Crystal oscillator circuit input pin (20 MHz) Crystal oscillator circuit output pin Test pin (connect to VSS) Description Continued on next page. No. 5784-4/7 LC895925 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin Pin Number 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Pin Name IO9 IO10 IO11 IO12 IO13 IO14 IO15 VSS RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 VDD VSS RAS0 RAS1 CAS0 CAS1 OE UWE LWE TEST0 VDD EXCK WFCK SBSO SCOR VSS BCK SDATA LRCK C2PO VDD VSS DB0 DB1 VDD DB2 DB3 VSS DB4 DB5 Type B B B B B B B P O O O O O O O O O O P P O O O O O O O I P O I I I P I I I I P P B B P B B P B B SCSI pins SCSI pins SCSI pins Serial data input clock input pin Serial data input pin 44.1-kHz strobe signal input pin C2 pointer input pin Subcode data read shift clock output pin Subcode frame synchronization input pin Subcode serial data input pin Subcode block synchronization input pin DRAM RAS signal output pins Address signal pins for ROM encoder/decoder DRAM Data signal pins for ROM encoder/decoder DRAM, with pull-up resistors Description DRAM CAS signal output pins DRAM Output Enable signal output pin DRAM Output Upper Write Enable signal output pin DRAM Output Lower Write Enable signal output pin Test pin (connect to VSS) Continued on next page. No. 5784-5/7 LC895925 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin Pin Number 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Pin Name VDD DB6 VDD VSS DB7 DBP VDD VSS ATN BSY VDD VSS ACK RST VDD VSS MSG SEL VDD C/D VDD REQ I/O VSS X1EN RESET VDD DATACKO PSUBSYNC EXTACK VDD VSS SUBSYNC FRCK FRCK EFM EFMGATE0 EFMGATE1 EFMGATE2 EFMGATE3 TEST5 VSS TEST6 Type P B P P B B P P B B P P B B P P B B P B P B B P I I P O O O P P O O O O O O O O I P I Test pin (connect to VSS) Test pin (connect to VSS) EFM pulse width detection gate signals Subcode synchronization signal output pin EFM frame synchronization signal output pin EFM output gate signal output pin EFM signal output pin 4.3218-MHz (Normal Speed) oscillator output pin Pseudo subcode synchronization output pin ATIP synchronization interval acknowledgment output pin Pin for selecting SCSI interface clock (XTALCK0 or XTALCK1) RESET pin SCSI pins SCSI pins SCSI pins SCSI pins SCSI pins SCSI pins SCSI pins Description Continued on next page. No. 5784-6/7 LC895925 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin Pin Number 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Name SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 VDD VSS D0 D1 D2 D3 D4 D5 D6 D7 VDD CS RD WR SWAIT INT0 INT1 Reserve3 Reserve4 Reserve5 VDD Type I I I I I I I P P B B B B B B B B P I I I O O O B B B P Reserved for future expansion (leave open) Chip select signal from microcontroller Data read signal from microcontroller Data write signal from microcontroller Wait signal to microcontroller Interrupt request signals to microcontroller. Open drain outputs with built-in pull-up resistors Microcontroller data signal pins, with pull-up resistors Command register selection address input pinsI Description s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. PS No. 5784-7/7 |
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